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DSIM Studio Simulation: No top-level element/configuration 'work.ALU_tb' found.
I already had success to run the tutorial of DSIM Simulation (VHDL code and Verilog testbench). Now I am trying to simulate my our example, but the simulation is failing with the error: "No top-level element/configuration 'work.ALU_tb' found." I already check all the files (top design and testbench) and everything looks…
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Dsim 2025.1 simulation example , carry_lookahead_adder fails on windows
I am trying to follow the introductory tutorial here but keep getting the following error Simulation time precision is 1ns.Linking image.so...dsim_work/obj/LR.o: file not recognized: File format not recognizedcollect2: ld returned 1 exit statusds_ld=N:linker exited with status: 1 Altair DSim version: 2025.1.0 (b:R #c:449…
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always_comb implicit sensitivity list
It seems that dsim includes in the implicit sensitivity list of always_comb the variables declared within the block . Consider the following simple code (I know that using nonblocking assignments in always_comb is not recommended, hower it is also not prohibited): `timescale 1ns/1ps module test; logic a,b, y; always_comb…
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unrecognized token before and spurious error
I've been having an issue with the errors i listed, this is output log with the dvlcom command dvlcom -incdir ../design:../testbench ../testbench/algn_apb_pkg.sv -lib alignerLib -uvm 1.2 Copyright (C) 2017-2025 Altair Engineering Inc. All rights reserved.=N:[UVMSource] Using sources from 'C:\Program…
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Running DSIM using Makefile
I am currently using Git Bash to be able to run Makefile's for dsim simulation, I need help because I am getting this error $ make analyze dvlcom -lib alignerLib -F ./filelist.txt C:/Progra~1/Altair/DSim/2025.1/bin/dvlcom.exe: error while loading shared libraries: libunwind.dll: cannot open shared object I think I set up…
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Dsim 2025.1 trying to make SSL connection despite dsim-license.json provided
Hi, I'm having trouble using DSim via command line as it tries to make an SSL connection to a license server. I have created an environment variable export DSIM_LICENSE=$HOME/metrics-ca/dsim-license.json I've verified it with echo $DSIM_LICENSE along with dsim -version returning 2025.1 Please advise. dsim hello.sv…
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DSIM is not able to solve constraint on valid code
On edaPlayground same code works on other simulators https://us.v-cdn.net/6038102/uploads/JFHZBNHJA9O7/array-constraint.sv
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Process is existing as a dreference error during the sim
class processtest; process p[]; event ev[]; function new(); p = new[5]; ev = new[5]; endfunction task start_prcess(int idx,int delay); fork begin $display("starting process for idx=%d tiem: %0t",idx, $time); p[idx] = process::self; wait(ev[idx].triggered); $display("process is done idx=%d time: %0t",idx, $time ); end…
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DSim 2025.1 Released
DSim 2025.1 has been released to the Altair Marketplace: https://altairone.com/Marketplace?tab=Download&app=DSim It includes the addition of support for UVM-3.1 and several bug fixes: https://help.metrics.ca/support/solutions/articles/154000226861-release-2025-1 Try it out and let us know what you think!
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DSIM License not obtained: Lease acquisition denied. Already at maxLease (1) for supplied license.
Description: DSIM License is not being obtained . after the simulation went into infinite loop Product/Topic Name : DSIM in DSIM. I wrote the code which went into infinite while loop by mistake. Once I killed VSCODE and refreshed the VSCODE. I am not able to run any simulation anymore and keep getting following error. $…
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Running DSim from command line
I'm using Ubuntu 24.04 on WSL and I have installed DSim there. I'm trying to run an UVM AXI VIP I found on GitHub. There is a makefile there and this makefile runs DSim from the command line. When I do “make” I get this error: dsim: error while loading shared libraries: libdummy_exports.so: cannot open shared object file:…
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DSim 2025.0.1 Now Available
DSim 2025.0.1 is now available in the Altair Marketplace: https://altairone.com/Marketplace?queryText=dsim&tab=Info&app=DSim This version fixes several issues with the initial release of DSim: https://help.metrics.ca/support/solutions/articles/154000221818-release-2025-0-1 If you have already installed a previous version…
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DSim error: "ld: cannot find C:\Program: No such file or directory"
I'm new to DSim Studio. When I try to simulate Altair's uvm-hello-world-main example I get the following error at the end of Elab1. I'm using Windows 11. Found 6 unique specialization(s) of 6 design element(s). Optimizing... Building models... PLI/VPI access: (none) Simulation time precision is 1ns. Linking image.so... ld:…
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Dsim: Syntax error when using macro in system verilog simulation
When compiling using Dsim, the compilation failed when it tried to compile this line. `define width 4 `define init 0 … count <= `width'd`init; By my understanding, the defined macro should be preprocessed before the compilation stage, so it should resolve to this: count <= 4'd0; It will be helpful if I can get away with…
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DSim Desktop Local Tool Installations - Failed to get list of versions
I have never used DSim before. I created a student account. I installed the extension for the Desktop version in VS Code and logged in to my account following the instructions, but when I try to install DSim I get the error in the screenshot. What should I do? Thank you.
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Installing DSIM cloud CLI (mdc) on Mac OS
I encountered an issue using DSim Cloud CLI on my Mac with an M3 processor. I found a workaround, and I'm creating this community note in case it helps others in the future. The issue: After installing DSim Cloud CLI, I got the following error when invoking the "mdc" executable: $ mdc --version bash: /usr/local/bin/mdc:…
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Port to MacOS
We have had customers request a port to MacOS. Please upvote this forum post if that would be something of interest to you.
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VPI support
Hi, The documentation mentions that DSim wants to support the VPI. I have been playing around with the VPI and tried DSim with cocotb. There seems to be issues regarding logging and get_sim_time callbacks: -.--ns TRACE gpi ../gpi/GpiCommon.cpp:616 in gpi_to_user Passing control to GPI user -.--ns TRACE gpi…
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Preprocessor output
Is there a way to inspect preprocessing output, such as text macro expansion, in DSim? IIRC, early versions of DSim shipped with a stand-alone SystemVerilog preprocessor, but there doesn't seem to be such a thing in recent releases.
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bug while parsing sdf file for annotation
Dsim fail with the attached example, as follows: dsim -top tb_test -sdf-verbose -timescale 1ns/1ps tb_test.sv =N:[UsageMeter (2025-02-04 15:00:09 +0100)] usage server initial connection =N:[License] Licensed for Metrics Design Automation. =N:[License] New lease granted. Analyzing... Elaborating... Top-level modules: $unit…
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Implicit port connection not properly checked
Consider the following simple Systemverilog code: module test (input logic clk, rst, output logic [3:0] cnt); always_ff @ (posedge clk) if (rst) cnt <= 0; else cnt <= cnt + 1; endmodule : test module tb_test; logic clk, rst; logic [3:0] cnt2; test mm (.*); // Error here initial begin rst = 1'b1; #3ns rst = 1'b0; #120ns;…
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Bug Report
I found the following bugs. 1. variables/objects declared below their reference point is not properly recognized in a class. Example) class my_class; //int a; // O.K function new(); a = 3; //this.a = 3; //O.K endfunction int a; // Compile Errorendclass The code above is complied normally if 'this' is not omitted. 2.…
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Bug: Applying a custom VHDL attribute to an array of records fails to compile
Compiling the following package fails in DSim version 20240422.0.0 with library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;package attribute_def_pkg is attribute type_length_attribute : natural; type record_type is record field_1 : std_logic; field_2 : std_logic; end record; attribute type_length_attribute…
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Mixed signal simulation dump file .mxd error
Hi, when working with a VHDL design with UVM environment so, doing mixed language simulation. I noticed that dumping the SystemVerilog BFM interfaces, VHDL DUT to .mxd file with the command : -waves <file_name>.mxd seems succesfull and end with no error. However, VHDL dump signals are only toggles between x and z when…
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Is there a method to save waveform signals and then reopen them in a new waveform window?
Hello everyone, I just wanted to know whether this feature is currently enabled or if it will be available in the future. It would be helpful to be able to save the signals and then reopen them in a new simulation. Thank you in advance. Ricardo
