I already had success to run the tutorial of DSIM Simulation (VHDL code and Verilog testbench). Now I am trying to simulate my our example, but the simulation is failing with the error: "No top-level element/configuration 'work.ALU_tb' found."
I already check all the files (top design and testbench) and everything looks good.
I don't know if there is any different configuration for VHDL testbench.
Can you help me to check if my files or my configuration are wrong?
