Bug: Applying a custom VHDL attribute to an array of records fails to compile
Compiling the following package fails in DSim version 20240422.0.0 with
library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;package attribute_def_pkg is attribute type_length_attribute : natural; type record_type is record field_1 : std_logic; field_2 : std_logic; end record; attribute type_length_attribute of record_type : type is 2; -- Works fine type array_of_records_type is array (1 downto 0) of record_type; attribute type_length_attribute of array_of_records_type : type is 4; -- Fails: E:[ClassHidden]end package attribute_def_pkg;
Best Answer
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Does this work on other simulators?
The declaration of array_of_records_type creates both a type and a subtype. The (anonymous) type is array(<>) of record_type, and the (named) subtype is array(1 downto 0) of record_type. When you provide the name array_of_records_type, you are actually targeting the subtype, not the base type. For this reason, the attribute specification is invalid.
The VHDL LRM is not the clearest work of prose, and it is possible that other tools let this slide, and treat types and subtypes as interchangeable for the purposes of assigning attributes.
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Answers
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Does this work on other simulators?
The declaration of array_of_records_type creates both a type and a subtype. The (anonymous) type is array(<>) of record_type, and the (named) subtype is array(1 downto 0) of record_type. When you provide the name array_of_records_type, you are actually targeting the subtype, not the base type. For this reason, the attribute specification is invalid.
The VHDL LRM is not the clearest work of prose, and it is possible that other tools let this slide, and treat types and subtypes as interchangeable for the purposes of assigning attributes.
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Hello David,
Thank you for the detailed explanation. Yes, this works using Questa-Sim (I tried with version 2022.4.4). GHDL however, fails as well, with an error message matching your explanation.
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