Dsim: Syntax error when using macro in system verilog simulation

alyee_tan920 · 2025-03-03T12:38:37+00:00

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Altair Community Member

Mar 3, 2025

When compiling using Dsim, the compilation failed when it tried to compile this line.

`define width 4

`define init 0

…
count <= `width'd`init;

By my understanding, the defined macro should be preprocessed before the compilation stage, so it should resolve to this:

count <= 4'd0;

It will be helpful if I can get away with using this way of coding as we are managing IP models running on multiple simulators from various vendors and currently other vendor simulator is able to support this code. I have attached a simple counter example on this error.

dsim_error.zip