Dsim: Syntax error when using macro in system verilog simulation

alyee_tan920
alyee_tan920 Altair Community Member
in Community Q&A

When compiling using Dsim, the compilation failed when it tried to compile this line.

`define width 4

`define init 0

…
count <= `width'd`init;

By my understanding, the defined macro should be preprocessed before the compilation stage, so it should resolve to this:

count <= 4'd0;

It will be helpful if I can get away with using this way of coding as we are managing IP models running on multiple simulators from various vendors and currently other vendor simulator is able to support this code. I have attached a simple counter example on this error.

dsim_error.zip
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Answers

  • Shaun_Altair
    Shaun_Altair
    Altair Employee

    DSim should resolve the defined macro properly. An internal bug report has been filed. I'll update you when the fix is available.

  • alyee_tan920
    alyee_tan920 Altair Community Member

    Hi Shaun, can we get an expectation on when will the fix be available? Thanks

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