Dsim: Syntax error when using macro in system verilog simulation
When compiling using Dsim, the compilation failed when it tried to compile this line.
`define width 4
`define init 0 … count <= `width'd`init;
By my understanding, the defined macro should be preprocessed before the compilation stage, so it should resolve to this:
count <= 4'd0;
It will be helpful if I can get away with using this way of coding as we are managing IP models running on multiple simulators from various vendors and currently other vendor simulator is able to support this code. I have attached a simple counter example on this error.
Best Answer
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DSim 2025.0.1 fixes this issue and can be downloaded from Altair Marketplace here:
If you don't want the installer to overwrite your existing DSim installation, please make sure to change the default installation path.
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Altair EmployeeAnswers
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DSim should resolve the defined macro properly. An internal bug report has been filed. I'll update you when the fix is available.
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Hi Shaun, can we get an expectation on when will the fix be available? Thanks
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Hello, I have to second that, we need this fixed ASAP. Any updates?
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More information: the provided test case fails with 20240923.8.0.
Interestingly enough, with version 20240422.0.0 the test case runs just fine!
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DSim 2025.0.1 fixes this issue and can be downloaded from Altair Marketplace here:
If you don't want the installer to overwrite your existing DSim installation, please make sure to change the default installation path.
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Hi Shaun, I have verified the issue is fixed in 2025.0.1, thank you so much.
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@alyee_tan920 Glad to hear it. Could you accept my previous post as the Answer to your question?
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