Implicit port connection not properly checked

Consider the following simple Systemverilog code:

module test (input logic clk, rst, output logic [3:0] cnt);
always_ff @ (posedge clk)
 if (rst)
   cnt <= 0;
 else
   cnt <= cnt + 1;
endmodule : test

module tb_test;
logic clk, rst;
logic [3:0] cnt2;

test mm (.*); // Error here

initial begin
    rst = 1'b1;
    #3ns rst = 1'b0;
    #120ns;
    $display("End of simulation");
    $finish;
end

always begin
    clk = 1'b0;
    #2ns;
    clk = 1'b1;
    #2ns;
end
endmodule : tb_test

There is an error in the implicit port connection: test mm (.*)  (due to the mispelled variable cnt2). However, this error is not reported by dsim that performs the simulation without signaling any error or warnings. Command issued:

dsim -noopt -timescale 1ns/1ps  +acc -waves test.vcd example.sv

Metrics DSim version: 20240923.0.0 (b:R #c:0 h:e981d301ee os:ubuntu_22.04)