Pollex signal integrity problem. SPice models
Description: Im new in PollEx and im trying to understand it, but when I try to simulate the "network analysis" it says "Spice run error".
The spice that i have are:
.SUBCKT irfz44n 1 2 3
- Model Generated by MODPEX *
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- Model generated on Apr 24, 96
- Model format: SPICE3
- Symmetry POWER MOS Model (Version 1.0)
- External Node Designations
- Node 1 -> Drain
- Node 2 -> Gate
- Node 3 -> Source
M1 9 7 8 8 MM L=100u W=100u - Default values used in MM:
- The voltage-dependent capacitances are
- not included. Other default values are:
- RS=0 RD=0 LD=0 CBD=0 CBS=0 CGBO=0
.MODEL MM NMOS LEVEL=1 IS=1e-32
+VTO=3.56214 LAMBDA=0 KP=39.3974
+CGSO=1.25255e-05 CGDO=2.2826e-07
RS 8 3 0.0133305
D1 3 1 MD
.MODEL MD D IS=9.64635e-13 RS=0.00967689 N=1.01377 BV=55
+IBV=0.00025 EG=1.08658 XTI=2.9994 TT=1e-07
+CJO=1.39353e-09 VJ=0.5 M=0.42532 FC=0.5
RDS 3 1 2.2e+06
RD 9 1 0.0001
RG 2 7 2.20235
D2 4 5 MD1 - Default values used in MD1:
- RS=0 EG=1.11 XTI=3.0 TT=0
- BV=infinite IBV=1mA
.MODEL MD1 D IS=1e-32 N=50
+CJO=1.52875e-09 VJ=0.5 M=0.584414 FC=1e-08
D3 0 5 MD2 - Default values used in MD2:
- EG=1.11 XTI=3.0 TT=0 CJO=0
- BV=infinite IBV=1mA
.MODEL MD2 D IS=1e-10 N=0.408752 RS=3e-06
RL 5 10 1
FI2 7 9 VFI2 -1
VFI2 4 0 0
EV16 10 0 9 7 1
CAP 11 10 2.06741e-09
FI1 7 9 VFI1 -1
VFI1 11 6 0
RCAP 6 10 1
D4 0 6 MD3 - Default values used in MD3:
- EG=1.11 XTI=3.0 TT=0 CJO=0
- RS=0 BV=infinite IBV=1mA
.MODEL MD3 D IS=1e-10 N=0.408752
For the MOSFET that is:
Answers
-
Dear Andreas,
I hope this message finds you well.
It seems there may be some misunderstanding regarding the intended use of PollEx in comparison to a standard circuit-level simulator. While PollEx does utilize a SPICE simulator in the background, its primary function is not to analyze transistor-level circuits. Instead, PollEx is specifically designed for signal integrity analysis, focusing on the digital communication between components. Mainly in terms of the impact comming from the layout structure. It provides fast and reliable simulations, with an emphasis on transitioning from the traditional SPICE approach to a piecewise linear (PWL) approximation for semiconductor behavior. This is achieved through IBIS and S-parameter models - going away from the SPICE-based transistor-level solutions.
In fact PollEx allows to use SPICE models - but only to some extend. The SPICE models interpreted by PollEx are typically dedicated to popcorn devices (Resistors, Capcitors, Inductors) and are composed of passive components and structures.
In addition, PollEx also supports power integrity simulations, which optimize the power delivery network. For these types of simulations, electronic component pins are modeled as voltage sources or current consumption points. Again, with no SPICE model involved.
For further details, I recommend referring to the PollEx training materials. You can find pre-recorded content in the "Learn" tab at the top of this page.
Thank you for your attention, and I hope this clears up any confusion.
Best regards,
Marek Jableka
Global Electronics Technical Team Manager0
Altair Employee