PSIM Gating Block for non-ideal MOSFET

Howdy PSIM users
I am using Gating blocks to generate unique patterns of PWM signals to drive switches in my converter.
This works well for ideal switches however I need to use the same PWM sequence for Level-2 MOSFET models, which is not supported.
Please advise.
Answers
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Hi,
For level2 MOSFE need to select "control to model" as shown in figure.
This might be one of the possible errors. Please check once.
Further, a detailed article on switches is available here:
PSIM switch models: Choose Wisely! — Altair Community
Thank you,
Vishwanatha Siddhartha
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Thank you for your response
I am aware of the "control to model" option in the on-off controller block.
I am using "a Gating block," which is like a lookup table on turn-on and off times.
I am using this because I am implementing a unique switching pattern, which cannot be emulated by voltage sources.
However it only allows direct connection to the gate of an ideal FET/ switch. It will not connect directly to a level 1/ 2 model or to an "on-off controller- multi-level" block.0 -
Hi,
It would be helpful to have the schematic file or any sample schematic, as it is difficult to fully understand this without it.
Thank you,
Vishwanatha Siddhartha
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Hi Oscar!
An alternative I can think of is using the piecewise linear source + a resistor. Another option is using a lookup table and a controlled voltage source. In both cases you would need to define points in time instead of an angle in degrees.
We'll ask around maybe there's another solution.
- Juan
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Hi all,
Based on Juan's comment, you could drive the gate like this:
The LuT should contain time vs Vgate info. You can find more details about LuTs here: https://community.altair.com/discussion/38451
BR,
Nikos
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Thank for the responses.
I am doing the following: As the "Gating block" can only drive ideal FETs, I am driving an ideal FET with it, and inverting the drain terminal voltage to the input of a "multi-level on-off controller".
A suggestion to the devs: the "Gating block" should have a mechanism of driving non-ideal FETs.0