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I have a variable called M which can take any value from 1 to 6. I want the value of S to take the value of 50, 60, 63.333, 276.67, 300, 1802.3 when M takes the values 1, 2, 3, 4, 5, 6 respectively. I.e. S = 63.333 when M = 3. Please could someone advise how I should do this.
Hi, The HM2024 model I'm working with has fasteners in different orientations. The analysis systems for the nodes attached to these fasteners have been updated to align with geometry. When exporting the FBD loads tables for all 14 load cases the first load case recognizes the correct CSYS but the remainder cases the loads…
Hi, I want to replicate some ANSYS model in HyperMesh. The model contains a hole where a bearing load is applied. In ANSYS software that load is easily applied with a dedicated command. However, I cannot replicate this in HyperMesh. Bearing loads are applied in the half-surface of a cylinder with a sinusoidal distribution…
We have had customers request a port to MacOS. Please upvote this forum post if that would be something of interest to you.
Hi, The documentation mentions that DSim wants to support the VPI. I have been playing around with the VPI and tried DSim with cocotb. There seems to be issues regarding logging and get_sim_time callbacks: -.--ns TRACE gpi ../gpi/GpiCommon.cpp:616 in gpi_to_user Passing control to GPI user -.--ns TRACE gpi…
Is there a way to inspect preprocessing output, such as text macro expansion, in DSim? IIRC, early versions of DSim shipped with a stand-alone SystemVerilog preprocessor, but there doesn't seem to be such a thing in recent releases.
Dsim fail with the attached example, as follows: dsim -top tb_test -sdf-verbose -timescale 1ns/1ps tb_test.sv =N:[UsageMeter (2025-02-04 15:00:09 +0100)] usage server initial connection =N:[License] Licensed for Metrics Design Automation. =N:[License] New lease granted. Analyzing... Elaborating... Top-level modules: $unit…
Consider the following simple Systemverilog code: module test (input logic clk, rst, output logic [3:0] cnt); always_ff @ (posedge clk) if (rst) cnt <= 0; else cnt <= cnt + 1; endmodule : test module tb_test; logic clk, rst; logic [3:0] cnt2; test mm (.*); // Error here initial begin rst = 1'b1; #3ns rst = 1'b0; #120ns;…
I found the following bugs. 1. variables/objects declared below their reference point is not properly recognized in a class. Example) class my_class; //int a; // O.K function new(); a = 3; //this.a = 3; //O.K endfunction int a; // Compile Errorendclass The code above is complied normally if 'this' is not omitted. 2.…
Compiling the following package fails in DSim version 20240422.0.0 with library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;package attribute_def_pkg is attribute type_length_attribute : natural; type record_type is record field_1 : std_logic; field_2 : std_logic; end record; attribute type_length_attribute…
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