Generating gate pulses for the secondary-side active bridge in resonant converters poses certain challenges, and multiple approaches exist to address them. In this article, we present an efficient and generalized method for generating secondary-side switching pulses that is applicable across a wide range of topologies, including half-bridge (HB) LLC, full-bridge (FB) LLC, and CLLLC resonant converters.
A key advantage of this approach is that it eliminates the need for current sensing, which simplifies hardware and improves system robustness. The method requires only a single feedback signal — the secondary-side voltage (Vsec) — as illustrated in Fig. 1.
Fig 1: Generalized resonant converter structure
The control algorithm (Homopolarity Cycle Modulation) for generating the gate pulses is shown in Fig. 2, while the corresponding PSIM-based implementation is presented in Fig. 3.
This implementation is based on the methodology proposed by Mohammadi and Ordonez in their recent IEEE publication: M. Mohammadi and M. Ordonez, titled "Synchronous Rectification of LLC Resonant Converters Using Homopolarity Cycle Modulation," published in IEEE Transactions on Industrial Electronics, vol. 66, no. 3, pp. 1781–1790, March 2019. DOI: 10.1109/TIE.2018.2840493
Fig 2: PWM generation logic for secondary side switches (Active Bridge II)
Fig 3: Control Implementation in PSIM
Important to remember:
- Monostable duration =
T0/2 = π * sqrt(Lr * Cr)
Here, we have used HCM (Homopolarity Cycle Modulation) and developed PSIM models.
Simulation Results (Active secondary vs Passive secondary):
In all simulations, the initial capacitor voltage was set to 420 V. Consequently, the simulation results start from this initial value of 420 V.
Fig 4: Output voltage at resonating frequency (Green-passive Bridge, Red-Active Bridge)
Fig 5: Output voltage at below resonating frequency (Green-passive Bridge, Red-Active Bridge)
Fig 6: Output voltage at above resonating frequency (Green-passive Bridge, Red-Active Bridge)
Simulation Files:
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