nav[aria-label="Primary Navigation"] { padding: 0; & ul { list-style: none; width: 100%; display: flex; flex-direction: row; justify-content: start; align-items: start; gap: 30px; padding: 0; & li { margin: 0; } & ul li { list-style: none; } } }

Siemens Community Catalyst Program

The Siemens Community Catalyst program was co-created with our community to acknowledge technology leaders who consistently contribute to the Siemens Community. Nominations are accepted on a rolling basis.

Nominate Now

How does PSIM determine the maximum allowable simulation time step?

Perapat

I would like to understand how PSIM determines the maximum allowable simulation time step for a circuit.

According to the PSIM documentation, the allowable maximum time step is calculated automatically and compared with the user-defined time step, and the smaller value is used for simulation. However, I have not found details on which circuit parameters or components are used in this calculation.

buck_ver1.psimsch

As an example, I attached a simple buck converter circuit. When I run the simulation, PSIM reports that the maximum allowable time step is 5e-9 s.

My questions are:

Is the time step based on switching frequency, PWM signal, device models, parasitic elements, or other criteria?
How can I identify which component or parameter in the circuit is limiting the time step to 5e-9 s?

I am using PSIM 2025 Student Edition.

Any explanation or references to the relevant documentation would be greatly appreciated.

Thank you.

Find more posts tagged with

PSIM

Accepted answers

All comments

There are no accepted answers yet