Altair slc simulate a single F-DQ channel with bit pattern test
Too long to post here, see github
GITHUB
https://github.com/rogerjdeangelis/utl-altair-slc-simulate-a-single-f-dq-channel-with-bit-pattern-test
Graphic output
PLOT
https://github.com/rogerjdeangelis/utl-altair-slc-simulate-a-single-f-dq-channel-with-bit-pattern-test/blob/main/bit_test.pdf
SIEMENS FORUM
https://support.industry.siemens.com/cs/document/109801902/
Conceptual setup
We model one F-DQ channel as a boolean output (True/False).
This is an oversiplified example but I think yo get the gist?
The bit pattern test” toggles this channel in a small sequence (e.g., [0,1,1,0]) once every
test period (simulating interval tests seen in real F-DQ modules).
WHAT WE WANT
Expected pattern: 1 0 1 0
Actual pattern: 1 0 1 0
VERIFIED: Pattern matches correctly
NO FAULTS DETECTED - All test cycles passed
= == == == == == == == == == == ==
F-DQ CHANNEL SIMULATION RESULTS"
= == == == == == == == == == == ==
actual and
time_step channel pattern test in_test
1 0 1 1 1 TRUE
2 1 0 0 0 TRUE
3 2 1 1 1 TRUE
4 3 0 0 0 TRUE
5 4 0 0 0 FALSE
6 5 0 0 0 FALSE
7 6 0 0 0 FALSE
8 7 0 0 0 FALSE
9 8 0 0 0 FALSE
10 9 0 0 0 FALSE
