code coverage causes to crash

Working dsim verification environment crashes when I gave the flag called "-code-cov a". Before giving that coverage flag it compiles and simulates perfectly. The crash comes from CGModule.cpp line 354. There is a assert statement that fails and crashes program with flag "=F:[Crash]". The verification environment includes nothing special or too complicated. It includes standard UVM components and trans_items plus RAL model with frontdoor and backdoor access to check how dsim works with RAL model. Design is SystemVerilog. Detailed log file can be found inside attachments. Configuration of project can bee from dpf file which is given below :

# Note: The contents of this file are automatically generated.

# Any changes made by hand may be overwritten.

version: '0.2'

work_dir: .

design_root_dir: .

simulations:

  - name: run_regTest

    options: >-

      -top uvc.tb_top -L dut -L uvc +acc+b -waves waves.mxd -uvm 1.2

      +UVM_NO_RELNOTES -sv_seed 365 -code-cov a

source_files:

  - language: verilog

    path: ./design.sv

    library_name: dut

    options: '-timescale 1ns/10ps'

  - language: verilog

    path: ./flist

    library_name: uvc

    options: '-uvm 1.2 +incdir+dir[+./.]'

    file_list: relative-to-file

library_search_paths:

  - $STD_LIBS\ieee93

I am using Windows 11 and Dsim version is 20240422.0.0