DSim crashed on array access

Maciej Dudek

Hi,

I was playing with DSim on the Linux system (DSim version 20240422.6.0)

and I found weird crash:

dsim: sv/SVBitSpan.cpp:99: bool dsim::sv::GetSIAndSpanFromExpr(dsim::sv::SVStoreItemRef&, dsim::sv::SVBitSpan&, dsim::sv::SVExprRef, bool): Assertion `0 && "can't refine span"' failed.

I've created small example that triggers this error.

test.v

Shona_altair

This bug has been fixed in DSim version 20240422.7.0. Please upgrade DSim and confirm that it fixes your issue.

Shaun_Altair

How did you compile test.v? I am unable to reproduce your issue because of the following parsing errors which occur when I execute `dsim test.v` and `dvlcom test.v`:

Analyzing...
=E:[ParseError]:
    Parser errors encountered at the following locations:    

    test.v:14:10    unrecognized tokens before '@'               

    test.v:16:18    unrecognized tokens before '<='              

    test.v:20:22    expected '.', '[', '('... instead of '<='    

    test.v:20:47    unrecognized tokens before ';'               

  Metrics DSim version: 20240422.6.0 (b:R #c:0 h:14d0e78ed1 os:msys2_)

Maciej Dudek

I'm running it with 

dsim -sv +acc+b -work dsim_run -genimage image test.v -timescale 1ns/1ps -j $(nproc) -top test

Shona_altair

Thank you for the specific command, I have been able to reproduce it and I'll look into the issue.  One of the optimizations is mis-handling something in your test.

You could try running without optimizations off (add `-noopt` to the command line)  as a short term work around.  It's not a satisfactory solution however, because without optimizations larger designs will be slow in simulation.

Shona_altair

We have found the issue, it will be fixed in our next release.  I will post an update here when it is available. 

Shona_altair

This bug has been fixed in DSim version 20240422.7.0. Please upgrade DSim and confirm that it fixes your issue.

Maciej Dudek

DSim requires `-sv` flag to be set to work

Shaun_Altair

The -sv option is required if the file extension is not .sv, as in your case. DSim will interpret .v files as Verilog and .sv files as SystemVerilog unless otherwise configured. See User Guide: DSim Input Filename Examples for details.