Use Verification to Ensure Protection Against Electrostatic Discharge

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Altair PollEx and Electrostatic Discharge

PollEx Design for Electrical (DFE) and Logic Design for Electrical (LDFE) are great tools when looking for design flaws or anticipating them. Their main purpose is to translate design conventions and accumulated knowledge to detect issues related to Signal Integrity, Power integrity, EMC, etc. Overall, these tools are excellent for complementing testing procedures.

The purpose of this blogpost is to show how PollEx can help detect that adequate protection for Electrostatic Discharge (ESD) exists on a PCB and that suppression components are both routed and placed correctly.

Let’s start with the basics, Electrostatic Discharge (ESD) is a sudden and brief flow of current between two electrically charged surfaces due to contact or dielectric breakdown. This is an issue that is very important for electronic devices that have an exposed connection outside of its housing. Since friction is a common way of electrically charging a surface, people tend to be the most common source of ESD due to the friction between the human body and surfaces like clothing, for example (Figure 1).

Figure 1. Technicians use ESD gloves to handle exposed electronics due to the human body being a source of ESD.

A discharge like this can greatly impair the function of an electronic device, and a common way to mitigate it is to redirect this current to ground before it reaches a vulnerable component. To do so, engineers place Transient Voltage Suppressor (TVS) Diodes between sensitive signal traces and the ground plane.

A TVS Diode is a clamping device that shunts current whenever the voltage rises above the breakdown voltage and then resets when the levels go back to normal. This is a great device to place on sensitive traces that are routed to a connector, which is a component that can introduce ESD currents into a PCB.  

To correctly control the flow of unwanted current through TVS diode some basic principles must be met, these are listed on Table 1,1- 4 and shown on Figure 2.

Table 1. Design principles for routing a TVS Diode

Figure 2. TVS Diode layout Example

Not following these principles or partially following them means an ESD event could still damage the victim device. Verification can help us detect a violation of these guidelines.

Schematic Verification with LDFE (Logic Design for Electrical)

The first approach is to assess the rules in Table 1 on a schematic level. PollEx offers verification for schematics with the LDFE (Logic Design for Electrical) tool. In this case, it can be used to verify the existence of TVS diodes and that they are correctly placed on ESD sensitive nets and with the correct polarity.

To show this, the schematic in Figure 3 is proposed . This schematic contains three circuits that are mostly the same, a connector that has a signal line connected to a microcontroller, but these differ in the following:  

• Circuit (a) has a TVS diode correctly placed.
• Circuit (b) has a TVS diode incorrectly placed.
• Circuit (c) has no TVS diode placed.

Figure 3. Test schematic.

To detect the existence and polarity of the diode the “Connected Comp” rule will be used. The basic function of this rule is explained in the image below (Figure 4).

This rule checks the connection between the following elements:

• User defined component (marked with blue)
• User defined net
• User defined polarity, specifying the connected pin.

Figure 4. Connected Component Rule Description

This rule requires the use of “Component Groups” and “Net Groups” to define the beforementioned elements of this check, which are defined by the user. With these groups, the automatic checks are focused on specific parts and nets. 

To define the contents of the “Component Groups” and “Net Groups” we can set up string filters and logical operators to find sensitive nets and the adequate protection components. This approach allows for the rule configurations to be reusable for any design and ensures that verification is always performed where it’s relevant.   

As expected, executing this rule shows PollEx detecting the incorrect placement of D2 and the missing diode of sensitiveNet_3. These results are shown in Figure 5.

Figure 5. LDFE Results Table

PCB Verification with PollEx Design for Electrical (DFE)

At the beginning of this blog, guidelines for the correct placement and routing of TVS Diodes were listed (see Table 1. and Figure 2).

The previous section has shown how to deal with these rules on a schematic level. In this section, PollEx DFE is used to check these guidelines at PCB level.

Like in the schematic example, a PCB with 4 basic topologies was designed (see Figure 5). These designs are as follows:

• Circuit (a) meets all the guidelines mentioned in Table 1.
• On Circuit (b) the diode is closer to the victim component than the connector, the trace is not routed directly to the pad of the TVS Diode, and it has a long trace to ground adding a lot of impedance to GND.
• On circuit (c) the TVS diode is not routed on the same side of the connector and doesn’t have stable grounding.
• On circuit (d) The TVS diode is not placed close to the connector, and it isn’t routed in the path of the connection.

Figure 6. Test PCB

Here the correct layout is circuit (a) where we meet all established design guidelines.

All the TVS design guidelines are presented in Table 1. can be addressed with "Passive Device Stability" rule on DFE (Figure 7)

Figure 7. “Passive Device Stability” rule on PollEx DFE

PollEx DFE benefits from the same flexibility as LDFE where the user can define “Component Groups” and “Net Groups” with filters so that the test can be easily reusable for different designs.

This rule requires "Component Group", Passive Component" and "Net Group" to be defined:

• "Start Device" would be a "Connector" (defined within "Component group")
• "Passive Component" is a "TVS diode" (defined within "Component group")
• "Target Nets" are the interconnections (defined within "Net Group") In figure n we see the configuration window of this rule, and we can see how the layout and routing guidelines are reflected.
• “End Component” (Shown in “Test Options” of Figure 8) would be an IC that needs protection (defined within "Component group")

Figure 8. “Passive Device Stability” rule configuration

To assess the design guidelines following steps were done:

• Establish maximum distance between the connector and the TVS Diode. To ensure that a diode exists as close to the ESD source as possible. (Table 1.1)
• Define the minimum polygon size for the GND pour to be a proper ground. (Table 1.4)
• Define the trace length of the GND trace. (Table 1.4)
• Toggle on the options: “Passive Component PAD should be connected to Net directly” and “Passive Component should be placed on the same layer with Component”. (Table 1.3 and Table 1.2 respectively)

Executing DFE results in outcomes depicted in table in Figure 9:

Figure 9. “Passive Device Stability” rule on PollEx DFE output

This rule correctly identifies the problem with each circuit. Table 2 has the results sorted by circuit and are interpreted as follows:

• Results for circuit b) indicate that the diode is too far away, not on the side of the connector and the path to GND is too long to be grounded correctly.
• Results for circuit c) are the same as circuit b). The key takeaway from this result is that this rule ignores that the diode is correctly routed if there’s a via before it, and it is placed opposite to the “Start Device”.
• Results for circuit d) indicate that the diode is too far away and not routed directly to the pad in the path between connector and victim component.

Table 2. “Passive Device Stability” organized result table

Conclusion

The solution to an electrical problem (in PCB design) lies in the layout and routing of the components in the design. Verification tools, through the analysis of the geometry of objects on the PCB, can detect bad practices that could result in non-compliance of electronic devices and in a worst-case scenario a total failure when it reaches customers’ hands. Not to mention, similar setup could be created to expand verification for multiple digital interfaces and protection devices.

In this blog, a rule from PollEx DFE and PollEx LDFE was used to verify that a protection component exists in a circuit that’s vulnerable to ESD and that said component is adequately placed and routed for it to work most efficiently.

PollEx offers a wide variety of checks covering many of the most common design issues that will be explored more, with additional content covering this topic on the horizon. In the meantime, learn more about PollEx applications at https://www.altair.com/pollex-applications.

List of abbreviations:

• Design for Electrical (DFE)
• Logic Design for Electrical (LDFE)
• Transient Voltage Suppressor (TVS) Diodes
• Electrostatic Discharge (ESD)