Mixed signal simulation dump file .mxd error

Hi, when working with a VHDL design with UVM environment so, doing mixed language simulation. I noticed that dumping the SystemVerilog BFM interfaces, VHDL DUT to .mxd file with the command :

-waves <file_name>.mxd

seems succesfull and end with no error. However, VHDL dump signals are only toggles between x and z when viewing dump file on VSCode which "x" and "z" states are impossible to occur because same .mxd file also consist of VIP SV interface signals which are properly working that includes clock, data, address etc. values respectively. This custom VIP would not behave properly and passes the test if there are "x" and "z" states all of the test. Dumping .vcd file and open it using vendor tools or GTKWave shows expected  proper VHDL design signals. So my question is:

Is it known issue that .mxd files can not be used for VHDL components. There is a section that called "How To: Simulate Mixed Language Simulation" and inside .vcd dumping is used but it is not defined whether it is recommended or obligation neither in user guide nor limitations. Or else is there a extra configuration related with mixed lang simulation fo VHDL related components to use metric extensible file as dump file.

 
I am going to share related dump files with you to if this case is unexpected, you might want to check it in your metric viewer. Also goint to share related screenshot.

I am using Dsim on Windows11. Dsim version is 20240422.0.0