Running a SystemVerilog testbench

mattioli

Hi,

Trying to run some basic testbench code in Dsim Studio I get the following errors:

=E:[UndefIdentifier]: Undefined identifiers:
top.sv:21:5 simple name: environment
=E:[IllegalMemberSelect]: A member-select(dot) operation is not valid for the given prefix types:
Prefix type Illegal suffix
top.sv:25:9 <error> testrun

Can't really see an error in code, please advice.

The test files attached

environment.sv

generator.sv

interface.sv

monitor.sv

scoreboard.sv

transaction.sv

top.sv

Shaun_Altair

Like I initially suspected from your error messages, your design files are not being included properly. "environment.sv" was not included in "top.sv", and all the files needed to create instances of the testbench components were not included in "environment.sv". All of these `include "filename" lines were actually in the design files from those testbench examples, but not in your design files. If you add them to your "environment.sv" and "top.sv", your design will compile and simulate correctly with Dsim. I have attached the log file for your review.

Also, in your Simulation Configuration Options, you do not need the "-L dut" switch, as you did not specify a library to compile your source files into, so they'll all be in the default library "work".

dsim_28Jan26.log

top.sv

environment.sv