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Hi,
Trying to run some basic testbench code in Dsim Studio I get the following errors:
=E:[UndefIdentifier]: Undefined identifiers: top.sv:21:5 simple name: environment =E:[IllegalMemberSelect]: A member-select(dot) operation is not valid for the given prefix types: Prefix type Illegal suffix top.sv:25:9 <error> testrun
Can't really see an error in code, please advice.
The test files attached
Like I initially suspected from your error messages, your design files are not being included properly. "environment.sv" was not included in "top.sv", and all the files needed to create instances of the testbench components were not included in "environment.sv". All of these `include "filename" lines were actually in the design files from those testbench examples, but not in your design files. If you add them to your "environment.sv" and "top.sv", your design will compile and simulate correctly with Dsim. I have attached the log file for your review.
Also, in your Simulation Configuration Options, you do not need the "-L dut" switch, as you did not specify a library to compile your source files into, so they'll all be in the default library "work".
@mattioli Did you follow the instructions in this support article on how to simulate UVM designs with Dsim Studio? The first step is often missed.
https://help.metrics.ca/support/solutions/articles/154000154284-how-to-use-uvm-in-dsim-studio
Without your Dsim Project File, *.dpf, we cannot reproduce your issue. I suspect your design files are not being included properly.
This testbench is pure SystemVerilog, no need for UVM. According to this methodology:
https://verificationguide.com/systemverilog/systemverilog-testbench/
Attached the dpf.
Okay, I had assumed it was a UVM design since those file names are typical of a UVM design. Looking at your *.dpf, you forgot to attach some files: consts.v, adder.v, driver.sv, etc. Please attach all the files required to compile and simulate your design.
My bad, forgot to mention it's without UVM. Missing files attached (except for consts,txt it is an empty file, can run without it).
Another example of SystemVerilog testbench posted here
https://verificationguide.com/systemverilog-examples/systemverilog-testbench-example-adder-2/
It works, thanks a lot!
@mattioli Glad to hear it. Can you mark my previous post as an Accepted Answer? Happy simulating!
