I am struggling with dumping waves from a VHDL simulation. When I look at the waves, I'm getting Xs and Zs instead of 0s and 1s:
I have attached the relevant files (I think). I cannot find anything about this in the documentation.
(In fact, I have regressed to a simpler VHDL simulation. The one I started with didn't record any waveforms at all at the testbench level, despite there being various std_logic signals and std_logic_vector signals.)
