VHDL wave dump

Eda Playground

I am struggling with dumping waves from a VHDL simulation. When I look at the waves, I'm getting Xs and Zs instead of 0s and 1s:

I have attached the relevant files (I think). I cannot find anything about this in the documentation. 

(In fact, I have regressed to a simpler VHDL simulation. The one I started with didn't record any waveforms at all at the testbench level, despite there being various std_logic signals and std_logic_vector signals.)

counter.vhd

Uploaded Feb 18, 2025782 B

countertb.vhd

Uploaded Feb 18, 20255.16 KB

ex07.dpf

Uploaded Feb 18, 2025390 B

Shaun_Altair

Not displaying VHDL signals properly in our Waveform Viewer is a known limitation which will be fixed in a future release.

See this post for details: https://help.metrics.ca/support/discussions/topics/154000634960

This limitation is documented in the DSim Desktop extension change log:

Shaun_Altair

The Metrics Waveform Viewer now properly displays VHDL signals in release v0.14.0 of DSim Desktop.

Shaun_Altair

@Eda Playground Does my comment above answer your question? The DSim Waveform Viewer properly displays VHDL signals in release 2025+ of DSim Studio.