Why doesn't the input match the output in the Digital Power ADC-DAC diagram?
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Answers
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Submitted by Anders89 on Sat, 05/11/2013 - 22:53.
The ADC and DAC blocks model the sampling delay and quantization error you get when using these devices. These are important concepts.
- Sampling delay – This is the time between ADC sample pulses plus the time for the ADC unit to convert an analog voltage into a 12 bit number. This delay time will causes phase lag in the feedback control and must be accounted for in any control system. These delays are settable in the ADC/DAC dialogs for the Digital Power ADC/DAC blocks.
- Quantization error - This is error induced when converting to/from the infinitely variable real-world to the fixed-bit width of the digital converter. In your example the ADC has 12 bits, so it can only represent 2^12 discrete intervals between the lowest and highest voltage. You have set 3.3v as VrefHi and 0 as VrefLo, so you can measure in 3.3/2^12 v (.0008v) intervals. The DAC has a 10-bit width and 0 .. 3.3v range, so will let you specify a voltage with an accuracy of 3.3/2^10 v (.0032v).
As you can see from your ADC simulation block settings below, your choice of a very slow ADC sample rate (100Hz) will result in large delay and dominates the error and is the primary cause of your steps on the DAC output. The hardware ADC conversion time on a typical C2000 is in the 200 nanosec range, in your dialog it is set to 10 microsecs, still quite small compared to the 10000 microsecs of your ADC sample rate so conversion time is not a factor in your diagram.
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