Double Pulse Testing is the standard method for measuring the switching parameters of MOSFETs or IGBT power devices.
Problem Statement: How to create a waveform as shown in Figure 1 when a trigger is sent?
One way to achieve the above-mentioned waveform is to run a timer thread at 1 µs and use the thread to toggle the GPIO on and off, but this is a computationally expensive task as thread is running at 1 µs. Also, if other functions / routines need to be run in the CPU, the timing of the actual switching moment of the GPIO output is very much dependent upon the actual CPU utilization and can occur at any point during the 1µs main routine rate and consequently, the required pulse-widths and timing would not be guaranteed.
Another way of achieving this waveform is using an ePWM peripheral on the microcontroller. The embed diagram titled “double_pulse_test.vsm” can be used to create the pulse pattern mentioned in the problem statement. This document will describe that model as shown in Figure 2.
The “enable PWM interrupt” compound block sets the registers to enable the PWM interrupt at the timer-base counter TBCTR = 0. On the first pass, a one-shot trip event on PWMA is executed to make sure the PWM output is in the off condition on startup. In the ePWM block as shown in Figure 3, the timer period is configured to set the PWM frequency to 125 KHz i.e., 8 µs period and in up/down counter mode.
The Action qualifier in the PWM dialog in figure 3 defines how to generate the PWM pulses. Compare A (CMPA) and compare B (CMPB) values corresponding to duty cycle values A and B are shown in Figure 4. When the PWM interrupt occurs at TBCTR = 0(Z), the “Re-arm” compound block checks if there is an input transition to enable the pulses, which is guaranteed to be seen within this block since the diagram frequency rate is << the PWM switching frequency. If a transition to enable the pulses is seen, the one-shot trip event is cleared. After which, while the PWM counter is counting up and CMPA is reached, GPIO0 (EPWM1A) goes to 1 and when CMPB is reached, it goes to zero again. In this way the first 1µs wide pulse is generated. When Period (P) is reached by the PWM counter, the GPIO0 goes returns to 1. While the PWM counter is counting down and the CMPB is reached, GPIO0 again returns to zero. In this way, a 2µs wide second pulse is generated. When the next PWM interrupt occurs at the next TBCTR = 0 event, there will be no transition on the input enable pulse, and the one-shot trip event will be re-triggered to stop any further pulse generation until another input enable pulse command occurs. In this way the double pulse test can be arbitrarily generated using minimal CPU resources.
The duty cycles A and B and the PWM frequency are variables which can be changed to modify the pulse characteristics.