How to create a variable time delay block like simulink

Ludowick MARIE-CLAIRE

Hello,

I simulate an active voltage rectifier unidirectionnal and i want to create a variable time delay with two signals. A référence sinus signal Vs (230 Volts 50 Hz) and the voltage at boundary of rectifier Vr. The DC part is a voltage source and the AC part is a voltage source Vs in serie with an smoothing inductor L. Vr = Vs+ VL. The current Is is the current at the input of circuit (Vs voltage source).

I found out : If you control the delay or phase différence of Vs compared to Vr and the amplitude of Vr, you can adjust the current Is et the phase of Is compared to Vs.

Rhonda_20369

There are many ways to implement this function. It all depends on how you plan to implement in your real engineering circuit.

In PSIM, you have the options to

 - Use some control blocks to build this function.

 - Use math function blocks

 - Use C block

 

PSIM simulation will help you to check whether your algorithm really works in the real world.