A place to ask questions about Altair products or solutions and receive help from community members or Altair employees. Don't forget to tag with the product/topic related to your question. Once you receive a satisfactory answer on your question, kindly mark your answers as "Accepted" so it can help others with similar problems.
I'm trying to use your simulator and I got a crash error when compiling SV/VHDL mixed environment. This is the sample env to reproduce this bug. https://gist.github.com/taichi-ishitani/97927543fa14edd95a84bd7f9be04115 You will see the crash report below during elaboration process. =F:[Crash] This Metrics software product…
As discussed in Is there a method to save waveform signals and then reopen them in a new waveform window? : Support (metrics.ca) I suggest adding this feature to allow us to reopen a simulation and load stored waveforms, instead of manually searching for them every time.
It would be nice if there is waveform reload function and a button for it on Waveform Viewer.Currently, we have to close Waveform Viewer and reopen updated *.mxd file on VS code once new simulation is run again and *.mxd file is updated. Shown signals should be kept even if the waveform file is reloaded.
Currently, event and string of SystemVerilog are not supported in *.mxd dump and its waveform viewing. It looks event is shown as level signal now and string doesn't appear on Waveform Viewer. It would be nice if event is shown as spike or so at its triggered time and string is properly shown as text. These are very…
Hello. i'm trying to learn the tool. i'm currently using Modelsim, i run all my simulation with TCL scripts. i would like to use DSIM the same way, from a script. i failed to find a scripting user manual. can someone help me? Thanks.
I am struggling with dumping waves from a VHDL simulation. When I look at the waves, I'm getting Xs and Zs instead of 0s and 1s: I have attached the relevant files (I think). I cannot find anything about this in the documentation. (In fact, I have regressed to a simpler VHDL simulation. The one I started with didn't record…
Hi, I've recently started working with some assertions in a project. All the assertions I am working with are designed to be evaluated in every posedge of the clk, but every time an assertion fails, the time reported in the log matches with a negedge in the waveform. Just for checking the behavior of the tool, I modified…
The provide Adder example works, but there is no clear explanation on what are the steps for creating a project from scratch. I tried by starting with one TB file where I am computing the factorial, but when I try to compile, I get the following error: "Source file "factorial.svh" from library "work" failed to compile with…
As of now I see DSIM Desktop is supported for some Linux distributions and Windows, is there a way to install DSIM on Mac OS?
Hi, I am trying to simulate the simulation example carry_lookahead_tb using DSIM locally on Ubuntu, but it does not work. The compilation process works, but when I try to run the simulation it always ends with the following error: Linking image.so... sh: 1: ld: not found ds_ld Metrics DSim version: 20240422.4.0 (b:R #c:0…
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